1. Field of the Invention
The present invention relates to a method of forming a semi-insulating region, and more particularly, to a method of forming a semi-insulating region applied to a radio frequency chip (RF chip) and integrated with very large scale integrated circuit (VLSI circuit) process.
2. Description of the Prior Art
The global wireless communication market is developing rapidly; the wireless communication business is thus becoming a rising star. Though the wireless communication products are different from each other due to the combinations of system configurations, user's applications, modulation methods, and channel receiving methods, the key components of them are typically comprised in the radio frequency/intermediate frequency integrated circuit (RF/IF IC) and the baseband integrated circuit (baseband IC). In the RF/IF IC, there is a low noise amplifier, a power amplifier, a voltage control oscillator (VCO), a phase lock loop, and passive and discrete devices, etc. In the baseband IC, there is a micro processor, a modulator and a demodulator, an A/D converter and a D/A converter, a digital signal processor (DSP), a memory device, and passive and discrete devices, etc.
Due to the demand of the market, the mobile communication vendors are all devoted to designing products with a cheaper price and smaller size. In other words, the mobile communication vendors try to integrate various components into an individual chip having a specific function, and eventually try to integrate various components into a single chip. While integrating all those components, not only the chip volume needs to be shrunk, but also the cost of the discrete devices could not be raised. In addition, the chip materials and the manufacturing process both impact the size and the cost of chip directly. It is necessary to prevent induced current, which is incurred from the coupling of each device and each integrated circuit on the chip, when applying in a radio frequency range so as to avoid degrading the electrical performance and the reliability of the communication chip.
Please refer to FIG. 1 to FIG. 2, FIG. 1 to FIG. 2 are schematic diagrams of fabricating a communication chip 28 according to the prior art. As shown in FIG. 1, the prior art communication chip 28 is fabricated on a semiconductor wafer 10. The semiconductor wafer 10 is usually a silicon wafer. A metal-oxide-semiconductor circuit (MOS circuit) 12, a micro-strip 14, and a high quality factor inductor (high Q inductor) 16 are comprised on a surface of the semiconductor wafer 10. The entire underside of the semiconductor wafer 10 is covered by a metal ground ring 18. An isolating region 22, disposed underneath the micro-strip 14 and the high quality factor inductor 16 in the semiconductor wafer 10, is disposed to fully decouple the micro-strip 14 and the high quality factor inductor 16 from the integrated circuit.
As shown in FIG. 2, a covering plate, composed of a metal material, is thereafter utilized as a mask 24 to irradiate the semiconductor wafer 10 with an x-ray beam 26. The x-ray beam 26 extends all the way through the whole thickness of the semiconductor wafer 10. The intensity of the x-ray beam 26 is between about 100 and 1,000 kGy/hr, and the photon energy of the x-ray beam 26 is between about 1 keV and 10 keV. The mask 24 is formed from high atomic weight metal materials, such as aluminum, iron, or tungsten. The mask 24, having a thickness of approximate 0.1 to 2 mm, only exposes the isolating region 22 to prevent the region outside the isolating region 22 in the semiconductor wafer 10 from being damaged.
When the semiconductor wafer 10 is irradiated with the x-ray beam 26, the structure along the irradiated path is damaged to increase the resistivity of the semiconductor material in the irradiated area by several orders of magnitude. As a result, the isolating region 22 in the semiconductor wafer 10 is transformed from semiconducting to semi-insulating. After performing some backend metallization process (not shown), the communication chip 28 is completed.
However, this method takes too much time (10 to 100 days). Therefore, another method was developed. Please refer to FIG. 3 to FIG. 4 that are schematic diagrams of fabricating another communication chip 46 according to the prior art. As shown in FIG. 3, the prior art communication chip is fabricated on a semiconductor wafer 30. The semiconductor wafer 30 is usually a silicon wafer. A metal-oxide-semiconductor circuit (MOS circuit) 32, a bipolar circuit 34, and an analog circuit 36 are comprised on a surface of the semiconductor wafer 30. Because it is necessary to decouple these different circuits from one another, two isolating regions 38 extending all the way through the semiconductor wafer 30 are necessary to be formed.
As shown in FIG. 4, a covering plate, composed of a metal material, is thereafter utilized as a mask 42 to irradiate the semiconductor wafer 30 with a high energy beam of particles 44. The high energy beam of particles 44 extends all the way through the whole thickness of the semiconductor wafer 30.
The high energy beam of particles 44 may be a proton beam. The intensity of the high energy beam of particles 44 is between about 1 and 10 microamps, and the particle energy of the high energy beam of particles 44 is between about 1 MeV and 30 MeV. The mask 42 is formed from high atomic weight metal materials, such as aluminum, iron, or tungsten. The mask 42 only exposes the isolating region 38 to prevent the region outside the isolating region 38 in the semiconductor wafer 30 from being damaged.
Similarly, when the semiconductor wafer 30 is irradiated with the high energy beam of particles 44, the structure along the irradiated path is damaged to increase the resistivity of the semiconductor material in the irradiated area by several orders of magnitude. As a result, the isolating region 38 in the semiconductor wafer 30 is transformed from semiconducting to semi-insulating. After performing some backend metallization process (not shown), the communication chip 46 is completed.
In the prior art methods, an isolating region having a significant depth is formed. Neither the conventional shallow trench isolation (STI) nor the field oxide layer (FOX layer), formed by the conventional local oxidation of silicon (LOCOS), is able to achieve such a depth. However, the prior art methods are not suitable for mass production at all since the photoresist layer utilized in the clean room, even the thick film photoresist having a thickness of approximate 200 to 300 μm, is unable to completely block the beam of particles with such a high energy. In the prior art methods, only a mask composed of metal material is disclosed. This kind of mask, although suitable for certain environments, is not suitable to be used in the clean room due to contamination issues.
However, to implant the communication chip with a beam of high energy particles to reduce the loss of silicon substrate, or the loss of another substrate is an inevitable process step. As mentioned previously, the total coupling problem needs to be resolved first to improve the high frequency performance of a communication chip to an acceptable extent, so as to be able to fabricate products with a wide application range. It is therefore very important to develop a method of forming a semi-insulating region. This method should be suitable to be performed in a clean room and in other environments. This method should utilize the photoresist layer, adapted widely in the clean room, or other substance as masks that are compatible with the manufacturing process of the integrated circuit, and should be integrated into integrated circuit processing to avoid the coupling problem and the inducing current problem when applied to communication chips. Furthermore, this method should be able to form the semi-insulating region with a three dimensional (3D) structure.